The invention relates to a storage device having an array of ferroelectric memory cells each containing information storing ferroelectric capacitors having a ferroelectric film as an insulator.
Ferroelectric materials have a characteristic that, once an electric polarization is created by an applied electric field, it remains even after the electric field is removed. Therefore, the polarization in a ferroelectric material will not be erased unless an opposite electric field of a certain intensity is applied to the material. Hence, it exhibits a hysteresis characteristic.
A ferroelectric memory, which utilizes ferroelectric capacitors for storing information and contains a ferroelectric film as an insulator, is a fast rewritable non-volatile memory, taking advantage of the ferroelectric property that it has a prolonged residual polarization and that it has a fast reversible speed (reversible within a few ns).
In addition, unlike EEPROM and flash memory which require a high voltage (about 10-12 Volts) in writing and reading data, a ferroelectric memory has a low reversion voltage (in the range of about 3-5 Volts). Hence, the ferroelectric memory can be operated by a low voltage power source.
FIG. 1 illustrates a ferroelectric storage device having a ferroelectric memory. This memory has a cell structure consisting of 2 transistors and 2 capacitors. (Such structure will be hereinafter referred to as 2Tr-2C cell structure). As shown in FIG. 1, the ferroelectric storage device includes: selection transistors Q00-Q11; ferroelectric capacitors C00-C11 for storing information; word lines WL0 and WL1 connected to the respective gates of the transistors Q00-Q11; bit lines BL0 and BL1; plate lines PL0 and PL1; and bit line capacitors Cbl representing parasitic capacitances of the bit lines BL0 and BL1. The selection transistor Q00, ferroelectric capacitor C00, selection transistor Q01, and ferroelectric capacitor C01 constitutes a memory cell MC0. A memory cell MC1 also has a similar structure. A memory array comprises a multiplicity of such memory cells. The storage device of FIG. 1 also includes a bit selection circuit 1 and a voltage detection means (sense amplifier, SA) for detecting a potential difference between two bit lines BL0 and BL1.
Data write and data read to such a ferroelectric memory cell as memory cell MC0 in a ferroelectric storage device are performed as follows. The same operation will be performed to other ferroelectric memory cells.
In a data write operation, the word line WL0 is raised to a high potential (HIGH) to turn on the selection transistors Q00 and Q01. At the same time the bit line BL0 is raised to HIGH, and the bit line BL1 to a low potential (LOW) by the bit selection circuit 1. Under this condition, the plate line PL0 is first pulled to LOW and then to HIGH and back to LOW again.
Through a sequential change in potential LOW-HIGH-LOW of the plate line PL0, the ferroelectric capacitor C00 coupled with the bit line BL0 is positively polarized, while the ferroelectric capacitor C01 coupled with the bit line BL1 is negatively polarized. This condition of the capacitors represents data xe2x80x9c1xe2x80x9d. To write data xe2x80x9c0xe2x80x9d, opposite potentials are given to the bit lines BL0 and BL1.
In a read operation, the plate line PL0 is initially set to LOW, and the bit lines BL0 and BL1 are set to LOW by the bit selection circuit 1 to precharge or bring the bit lines to 0 Volt. The bit lines BL0 and BL1 are then floated by a signal from the bit selection circuit 1. The word line WL0 is set to HIGH to turn ON the selection transistors Q00 and Q01. Under this condition, the ferroelectric capacitor C00 and the bit line capacitor Cbl coupled with the bit line BL0 are connected in series, while the ferroelectric capacitor C01 and the bit line capacitor Cbl coupled with the bit line BL1 are connected in series.
Next, the plate line PL0 is pulled HIGH, so that the bit lines BL0 and BL1 acquire respective potentials determined by the electrostatic capacitances of the ferroelectric capacitors C00, C01 and the bit line capacitor Cbl. Then the polarization of the ferroelectric capacitor C00 coupled with the bit line BL0 is reversed if the data stored in the memory is xe2x80x9c1xe2x80x9d, thereby generating a relatively high potential on the bit line BL0. On the other hand, the polarization of the ferroelectric capacitor C01 coupled with the bit line BL1 will not be reversed, yielding a relatively low potential on the bit line BL1.
The potential difference between the two bit lines BL0 and BL1 is detected by the sense amplifier SA, thereby distinguishing between xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d as follows:
Read data is recognized as xe2x80x9c1xe2x80x9d if the potential difference (BL0xe2x88x92BL1) greater than 0.
Read data is recognized as xe2x80x9c0xe2x80x9d if the potential difference (BL0xe2x88x92BL1) less than 0.
Since data read from a memory that utilizes ferroelectric capacitors destroys the data stored in the memory, each of the bit lines BL0 and BL1 is set to HIGH or LOW, depending on the data stored, to restore the data in the memory. For example, the bit lines BL0 and BL1 are set to HIGH and LOW, respectively, when the data is xe2x80x9c1xe2x80x9d.
So far 2Tr-2C cell structure of a ferroelectric storage device has been discussed. A ferroelectric storage device utilizing one transistor and one capacitor (referred to as 1Tr-1C structure) is also known. Such 1Tr-1C cell structure ferroelectric storage device is provided with a reference voltage generation means for providing a reference voltage to detect the difference in voltage generated on two bit lines at the time of data read. Data read operation for the 1Tr-1C cell structure device is essentially the same as for 2Tr-2C cell structure device.
Since in the ferroelectric storage device that uses a memory array of ferroelectric capacitors the content of a memory cell is determined by the potential difference between two bit lines, it is necessary that a voltage margin is secured for data read.
Conventionally, tests are performed on a ferroelectric storage device during manufacturing and a test period by screening each memory cell before and/or after it is packaged. In the tests a memory is determined to be defective or not by checking if data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d can be correctly written to and read from the memory. However, such conventional tests cannot assess operational margin of the storage device that has passed the tests, so that the test cannot verify if the memory has a desired operational margin as designed or not.
Therefore, it is an object of the invention to provide a reliable ferroelectric storage device having an array of ferroelectric memory cells, by measuring bit line voltages that arises from the electric charges remaining in the ferroelectric memory cells, thereby quantitatively assessing deviations in characteristics and degree of defect/degradation of the ferroelectric capacitors in the cells.
In accordance with one aspect of the invention, there is provided a ferroelectric storage device having 2Tr-2C cell structure, comprising:
memory cells each including
a first ferroelectric capacitor C0 connected in series with a first selection transistor Q0 which is selected by a word line WL; and
a second ferroelectric capacitor C1 connected in series with a second selection transistor Q1 which is selected by the word line, the first and second ferroelectric capacitors having opposite polarization;
a first bit line BL0 connected to one end of the series connection of the first ferroelectric capacitor C0 and the first selection transistor Q0 and having a bit line capacitor Cbl;
a second bit line BL1 connected to one end of the series connection of the second ferroelectric capacitor C1 and the second selection transistor Q1, and having a bit line capacitor Cbl;
a plate line PL connected to the other end of the series connection of the first ferroelectric capacitor C0 and the first selection transistor Q0 and to the other end of the series connection of the second ferroelectric capacitor C1 and the second selection transistor Q1, the plate line adapted to provide a predetermined voltage;
a voltage detection means SA connected between the first bit line and the second bit line;
an external reference voltage input terminal Tvref for receiving an external reference voltage Vref-ext;
a first control switch means Q10 provided between the external reference voltage input terminal and the first bit line, and switchable between ON and OFF by a first test signal TESTO; and
a second control switch means Q11 provided between the external reference voltage input terminal and the second bit line, and switchable between ON and OFF by a second test signal TEST1.
In this arrangement, only one of the first and the second control switch means can be selectively turned ON by the first or the second test signal.
In this screening test of a ferroelectric storage device having 2Tr-2C cell structure, only one of the test switches Q10 or Q11 is turned ON to supply a regulated reference voltage Vref to one end of the voltage detection means (sense amplifier) SA. Repetition of the test for different reference voltages Vref provides quantitative determination of the characteristics of the ferroelectric capacitor C0 (or C1) through measurement of the bit line voltage input to the other input end of the voltage detection means. The measurement provides assessment of deviations in characteristics and degrees of defect/degradation of the ferroelectric capacitors, thereby enabling improvement of the reliability of the ferroelectric storage device.
In another aspect of the invention, there is provided a ferroelectric storage device having 1Tr-1C cell structure, comprising:
memory cells each including a ferroelectric capacitor C0 connected in series with a selection transistor Q0 which is selected by a word line WL;
a bit line BL connected with one end of the series connection of the ferroelectric capacitor and the selection transistor, and having a bit capacitor Cbl;
a plate line PL connected with the other end of the series connection of the ferroelectric capacitor and the selection transistor, and adapted to provide a predetermined voltage;
a reference voltage generation circuit 2 for generating a reference voltage Vref;
an external reference voltage input terminal Tvref for receiving an external reference voltage Vref-ext;
a voltage detection means SA having one end connected to the bit line;
first control switch means Q12 connected between the other end of the voltage detection means SA and the external reference voltage input terminal, and adapted to switch between ON and OFF in response to a test signal TEST; and
second control switch means Q13 connected between the other end of the voltage detection means SA and the reference voltage generation circuit, and adapted to be switchable between OFF and ON in response to a test signal.
Only one of the first and second control switch means can be selectively turned ON by the test signal.
In this arrangement, as the first control switch means Q12 provided between the external terminal Tvref and the bit line BL is turned on, an external regulated reference voltage Vref is supplied to one end of the voltage detection means SA in the screening test of 1Tr-1C cell structure ferroelectric storage device. The bit line voltage supplied to the other end of the voltage detection means SA, i.e. characteristic voltage of the ferroelectric capacitor C0 may be quantitatively determined by regulating the external reference voltage Vref.
Thus, deviations in characteristics and degrees of defect/degradation of the ferroelectric capacitors can be precisely evaluated, thereby enabling increasing reliability of the ferroelectric storage devices. The reference voltage of an external reference voltage generation circuit 2 can be set to a proper level by regulating the output voltage of the reference voltage generation circuit 2 based on the quantitatively measured characteristics of a ferroelectric capacitor C0.
In accordance with a further aspect of the invention, there is provided a ferroelectric storage device having 1Tr-1C cell structure, comprising:
memory cells each including a ferroelectric capacitor C0 connected in series with a selection transistor Q0 which is selected by a word line WL;
a bit line BL connected to one end of the series connection of the ferroelectric capacitor and the selection transistor, and having a bit line capacitor Cbl;
a plate line PL connected to the other end of the series connection of the ferroelectric capacitor and the selection transistor, and adapted to provide a predetermined voltage;
a reference voltage generation circuit 2xe2x80x2 for generating a reference voltage Vref;
voltage detection means SA connected between the bit line and the reference voltage generation circuit, wherein the reference voltage generation circuit 2xe2x80x2 includes
memory means 3 storing a multiplicity of voltage data in digital form;
a digital-analog converter 4 for converting the digital voltage data received from the memory means into an analog signal and outputting the analog signal as the reference voltage; and
a controller 5 for instructing the memory means of voltage data to be output therefrom.
The memory means 3 may have ferroelectric memory cells of 2Tr-2C structure.
All the memory cells of the ferroelectric storage device 11 may be categorized into a multiplicity of memory cell regions 11-1 through 11-n such that each region is provided with a corresponding memory means 3-1 through 3-n and a corresponding digital-analog converter 4-1 through 4-n.
In this arrangement, in the screening test of the ferroelectric storage device having 1Tr-1C cell structure, a regulated reference voltage Vref based on the multiple voltage data stored in the ferroelectric memory means 3 is supplied from the reference voltage generation circuit 2 to one end of the voltage detection means (sense amplifier) SA. Thus, by repeating the test for different regulated reference voltages Vref supplied by the reference voltage generation circuit 2, quantitative assessment of characteristics of the ferroelectric capacitor C0 can be made through the measurement of the bit line voltage input to the other end of the voltage detection means SA.
In this manner, precise deviations in characteristics and degree of defect/degradation of ferroelectric capacitors can be obtained, which provide necessary information to improve the reliability of the ferroelectric storage device. It is possible to set an adequate reference voltage for the ferroelectric storage device by regulating the output voltage of the reference voltage generation circuit 2 based on the characteristics of a ferroelectric capacitor C0.
It is noted that the memory means 3 has a larger margin for defect/degradation as compared with ferroelectric storage memory having 1Tr-1C cell structure, since memory means 3 has 2Tr-2C structure memory cells. Accordingly, the memory means 3 has a higher reliability as a storage device.
Memory cells may be classified into different memory cell groups 11-1 through 11-n in accordance with the degree of deviations in characteristics as determined by screening tests, and an appropriate reference voltage Vref may be given to the sense amplifier SA for each group.